Metal-Oxide-Silicon (MOS) devices and complementary MOS (CMOS) circuit structures have become dominant in the fabrication of circuitry for digital processing. Integrated circuits (IC) have become increasingly powerful in circuit density and circuit speed has increased. To accomplish this improvement, technologists have been able to continue this trend by device scaling and by improving materials and IC fabrication processes.
As devices have become smaller, process variations have a much greater affect on circuit performance variability and thus it is more difficult to predict the performance of an IC and thus the system in which it is intended to function.
MOS devices are basically voltage controlled current switches. The gate voltage determines how much current flows in the channel somewhat independent of the voltage across the channel from source to drain. Using the CMOS structure where there is no static power dissipation (excluding leakage) the current from an ON device is used to charge or discharge the capacitance of the gate(s) of following circuits. The drain current in a MOS device is inversely proportional to the effective channel length (Leff) and directly proportional to the difference between the gate-to-source voltage (VGS) and the devices threshold voltage (VT). VGS is usually an applied voltage and VT is an intrinsic parameter which is a function of the fabrication process and its variations. To complicate matters Leff and VT are interdependent.
To accurately design a MOS fabrication process, it is necessary to isolate each parameter VT and Leff and understand what process steps are causing their variability (variance). Both of these parameters affect drain current and are difficult to directly determine as device sizes have gotten smaller, therefore, the variance of these parameters are not independently determined.
Prior art has used devices with larger channel lengths in an attempt to assure there is no Leff variability as a way of removing the interdependence of Leff and VT. However, since variance of VT due to dopant fluctuation also depends on gate area, there can be no comparison of devices with different gate areas. Others have tried to building test sites with different channel lengths but with the same gate areas. Critical dimension (CD) metrology has also be attempted but it is an expensive process.
Therefore, there is a need for a method that uses automatic testing measurements to accurately and efficiently separate the variance of threshold voltage VT with respect to dopant levels and the variance of the effective channel length Leff to allow these parameters to be controlled as scaling reduces chip device geometries.